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Category:1951 births
Category:Living people
Category:Venezuelan male weightlifters
Category:Weightlifters at the 1988 Summer Olympics
Category:Weightlifters at the 1992 Summer Olympics
Category:Olympic weightlifters of VenezuelaThe present invention relates to an integrated circuit, in particular for very large scale integrated circuits (VLSI), including a series of MOS transistors.
As is known, VLSI comprises a large number of MOS transistors (typically greater than 5.times.10.sup.6) integrated on a single substrate by means of a CMOS (complementary MOS) process. In general, on the same substrate there are also other MOS transistors, which are not directly concerned with the readout circuit of the memory, e.g. for the control of the memory or for the scanning of the rows.
In the memory, in particular in a DRAM memory, a plurality of word lines and a plurality of bit line pairs, with suitable control devices, are connected to a plurality of MOS transistors whose respective gates are cross-connected with respect to those of the MOS transistors connected to the selected word lines. Generally, in the memory, the plurality of MOS transistors are N-channel MOS transistors.
It is essential to ensure electrical insulation of the substrate of the memory matrix from the control circuit, which is generally made from P-channel MOS transistors. This insulativity is achieved by placing a PN-junction between the substrate and a well region, which is of opposite conductivity type to that of the substrate, to provide the proper substrate bias voltages.
In the above VLSI, in order to enable the normal operation of the MOS transistors of the readout circuit and to ensure proper protection against malfunctions, the substrate bias voltages must be set to a predetermined value.
In the commonly used circuits, this is achieved by using an auxiliary region (well of opposite conductivity type) adjacent to the substrate and, if the VLSI is “off”, by bringing this auxiliary region to an appropriate bias state. In other words, the supply voltage V.sub.cc of the control circuit is supplied to the substrate through the auxiliary region. The substrate bias voltages are then supplied by means of suitable MOS transistors in the various memory


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\ the stained samples were mounted on glass slides with a coverslip. The slides were examined by fluorescence microscopy (Olympus America Inc., Center Valley, PA, USA) to confirm the presence of Mitotracker Green inside the mitochondria.

Quantitative analysis of ROS

Cells in the control, 1, 3, and 7 days after ischemic induction were stained with DCF-DA for ROS measurements. Fluorescence was detected using a fluorescent microscope (Olympus America Inc., Center Valley, PA, USA). The amount of ROS was expressed as the fold change from the cells in the control.

Measurement of mitochondrial membrane potential

Mitochondrial membrane potential was detected by loading the cells with JC-1 dye. The distribution and changes in mitochondrial membrane potential were determined by flow cytometry analysis. The cells were examined by flow cytometry in three different groups: 1, 3, and 7 days after the induction of ischemic injury.

Cell viability measurements

The effect of ischemic injury on cell viability was determined by measuring the cellular 3-(4,5-dimethylthiazol-2-yl)-2,5-diphenyltetrazolium bromide (MTT) activity. According to the manufacturer’s directions, the control cells were incubated with MTT solution. The formazan crystals that formed were dissolved in 50 μL dimethyl sulfoxide and added to the wells. The absorbance was measured at 490 nm on a plate reader (Bio-

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